Speaker
Dr
Satoshi Matsuoka
(Tokyo Institute of Technology)
Description
The so-called “Moore’s Law”, by which the performance of the
processors will increase exponentially by factor of 4 every 3 years or
so, is slated to be ending in 10-15 year timeframe due to the
lithography of VLSIs reaching its limits around that time, and combined
with other physical factors. This is largely due to the transistor power
becoming largely constant, and as a result, means to sustain continuous
performance increase must be sought otherwise than increasing the clock
rate or the number of floating point units in the chips, i.e., increase
in the FLOPS. The promising new parameter in place of the transistor
count is the perceived increase in the capacity and bandwidth of storage,
driven by device, architectural, as well as packaging innovations:
DRAM-alternative Non-Volatile Memory (NVM) devices, 3-D memory and logic
stacking evolving from VIAs to direct silicone stacking, as well as
next-generation terabit optics and networks. The overall effect of this
is that, the trend to increase the computational intensity as advocated
today will no longer result in performance increase, but rather,
exploiting the memory and bandwidth capacities will instead be the right
methodology. However, such shift in compute-vs-data tradeoffs would not
exactly be return to the old vector days, since other physical factors
such as latency will not change. As such, performance modeling to
account for the evolution of such fundamental architectural change in
the post-Moore era would become important, as it could lead to
disruptive alterations on how the computing system, both hardware and
software, would be evolving towards the future. We are now in the
process of launching such innovative projects for the future of
computing in Japan
Primary author
Dr
Satoshi Matsuoka
(Tokyo Institute of Technology)
